Implementation of DSP standard cells based on residue number system.

The work presented in this thesis was partially for fulfilling contract requirements with Communication Research Centre (CRC). The objectives of this contract were the investigation and implementation of DSP macrocells based on Residue Number System (RNS) in MOSIS CMOSN technology. The macrocells suggested for implementation are based on a bit-level inner product processor (BIPSP$\sb{\rm m}$) developed in the VLSI Research group by Taheri et al. The layout of this cell was perfected by Del Pup. The BIPSP$\sb{\rm m}$ cell design is a modification of the existing design to conform to the MOSIS CMOSN technology. Special emphasis is placed on fault detection and correction. The fault detection scheme suggested by Taheri has been incorporated in the BIPSP$\sb{\rm m}$ cell design. As part of the work presented in this thesis, is an introductory chapter on Residue Arithmetic. Also presented in this thesis is a compilation of research in the area of residue computational hardware, covering the earliest works to most recent developments in this area. Additionally a great part of the time spent on this thesis was to establish a working environment for the MOSIS CMOSN process, using the design tools available at the VLSI Research Lab, namely Cadence Edge$\sp{\rm TM}$. The macrocells designed, discussed and implemented include encoders, decoder/scalers, adders, multipliers, 2-D FFT butterfly and FIR filters.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1994 .S525. Source: Masters Abstracts International, Volume: 33-04, page: 1312. Supervisor: G. A. Jullien. Thesis (M.Sc.A.)--University of Windsor (Canada), 1994