Steiner tree and interconnect optimization in VLSI design.

One of the key problems in VLSI interconnect design is the topology construction of signal nets with minimum cost. Steiner tree problem is to find the tree structure that connects all pins of a signal net such that the wire length can be minimized. Since Steiner tree problem is NP-hard, many different heuristics and approximation algorithms have been derived to deal with this problem. However, in VLSI design automation the routing is performed in the presence of obstacles, such as logic cells, where the wires of the net must not intersect. Most of the previous heuristics deal with problems under the assumption that wires do not cross any obstacles. In this study, a class of probabilistic approaches to Steiner tree problem has been extensively explored, which is able to construct Steiner tree with good performance in term of wire length or speed, and able to solve the problem in presence of obstacles. Probabilistic model and a series of algorithms based on it have been established and implemented. Extensive experiments conducted on both small- and large-size problems have been designed to show the performance comparison with the state-of-the-art algorithm. How to deal with blockage and congestion in probabilistic algorithms has been discussed. Also, an optimization algorithm has also been presented, which improves wire length from the results of probabilistic algorithms as well as any other algorithms. In addition, the potential advantages with our approaches are also discussed for further applications.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2002 .Z44. Source: Masters Abstracts International, Volume: 41-04, page: 1162. Adviser: Chunhong Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2002