VLSI IMPLEMENTATON OF RESIDUE NUMBER SYSTEM ARCHITECTURES.

This work is an investigation into the use of Residue Number System (RNS) architectures in the Very Large Scale Integration (VLSI) medium. The work proposes RNS models, design methods, and system architectures for Digital Signal Processing (DSP) applications. A new look-up table layout model is developed, which is valid for any modulus. It is used to estimate both area and time required for implementing modulo look-up tables. Using the model, a look-up table layout procedure is developed to select the most efficient layout according to the design requirements. A new abstract model, devoted to RNS systems, is shown to provide asymptotic bounds for large moduli systems. A new set of building block modules are proposed, they are based on storing several independent look-up tables in the same chip with appropriate interconnections. Several procedures have been developed to optimize the layout of these modules. A binary adder design method is given to support RNS modules based on a binary adder. Two new structures for implementing FIR digital filters have been described; both structures employ systolic arrays. The first structure is based on the look-up table approach, while the second combines both look-up tables and combinatorial elements. The second structure is efficient for large moduli and large set of data. Both highly modular structures employ pipelining in order to maximize the throughput rate. Source: Dissertation Abstracts International, Volume: 46-08, Section: B, page: 2751. Thesis (Ph.D.)--University of Windsor (Canada), 1985