The design and simulation of parallel DSP architectures for adaptive and frequency domain image-processing applications

Includes bibliographical references (pages [65]-66)It is well known that because of the large amount of data involved, the execution of image-processing algorithms consume a considerable amount of processing time. Hence, image-processing applications utilize hybrid systems composed of array processors for speed enhancement coupled with high-speed computers for flexibility. The processing-time problem becomes even more acute when the image has to go through several preprocessing stages before the final processing can be done. The main objective of the work presented in this thesis was to try and speed up several specific adaptive algorithms and transforms which are generally used in the preprocessing stages of image-processing applications. The speedup of these algorithms was achieved by implementing them in parallel on Tightly Coupled multiple Digital Signal Processor (DSP) architectures. The final objective of this work was to develop generalized parallel DSP architectural setups which could be interfaced to an existing image-processing system, the FG-100-AT, and implement a specific class of image-processing algorithms (adaptive / frequency transforms / adaptive+frequency transforms). In the subsequent chapters, the architectural setup for adaptive (one-dimensional and two-dimensional) image-processing, the architectural setups for transform domain image processing, and the generalized setup for both these classes are discussed. The adaptive LMS and the two-dimensional Hartley Transform is implemented in parallel on these architectural setups. The effectiveness of these setups is depicted with the help of speedup and Processor Utilization Curves.M.S. (Master of Science