On the limit of the output capacitor reduction in power factor correctors by distorting the line input current

Active power-factor correctors (PFCs) are needed to design ac-dc power supplies with universal input voltage range and sinusoidal input current. The classical method to control PFCs consists in two feedback loops and an analog multiplier. Hence, the input current is sinusoidal and it is in-phase with the input voltage. However, a bulk capacitor is needed to balance the input and the output power. Due to its high capacitance, an electrolytic capacitor is traditionally used as a bulk capacitor in PFCs. As a consequence, the lifetime of the ac-dc power supply is limited by the electrolytic capacitor's, which becomes insufficient to some applications (e.g., high-brightness LEDs). This paper proposes a reduction of the output voltage ripple (which allows reduction of the output capacitance) by distorting the input current, but maintaining the harmonic continent compatible with EN 61000-3-2 regulations. The limits of this output capacitor reductions are deduced. Also, a control strategy based on a low-cost microcontroller is developed to put the proposed study into practice. Finally, the theoretical results are validated in a 500-W prototyp