High bandwidth memory interface design based on DDR3 SDRAM and FPGA

This work presented the high bandwidth memory interface design based on DDR3 SDRAM using external memory IP core provided by FPGA devices. The structure and configuration of IP core was introduced and the simulation on soft and hard IP was carried out with the access controller designed. The maximum transmission bandwidth of the memory interface based on the soft and hard IP respectively reached 19.2Gbps and 25.6Gbps. Finally, the reliability of the interface controller was verified by downloading the program to the DAQ board and observing the internal signals