Bandwidth Design for CMOS Monolithic Photoreceiver

A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade(RGC) transimpedance amplifier (TIA) is designed. The small signal circuit model of DPD is given and the band width design method of a monolithic photoreceiver is presented. An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail. A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0. 6um CMOS process and the test result is given