A combinatorial problem that arises from a novel electronic fabric architecture designed forlow-power devices such as cellular phones and palm computers is presented. We consider theproblem of efficiently mapping a given data flow graph onto a particular implementation ofthe fabric architecture. We formulate mixed integer linear programs (MILP) and design asliding partial MILP heuristic for this problem. We highlight the modeling and algorithmicaspects that are necessary to make the MILP formulation competitive. The sliding partialMILP heuristic is developed to generate mappings faster and to find mappings for benchmarkinstances that cannot be solved by the MILP formulation.We also present a method to tune software parameters using ideas fr...
[[abstract]]We combine technology mapping and placement into a single procedure, M.map, for the desi...
Field Programmable Gate Array (FPGA)-like programmability and Computer Aided Design (CAD), with Appl...
This paper describes a technique for calculating the switching activity of a set of registers shared...
A combinatorial problem that arises from a novel electronic fabric architecture designed forlow-powe...
Application specific programmable systems are capable of high performance implementations while rema...
[[abstract]]We study the technology mapping problem for LUT-based FPGAs targeting at power minimizat...
This paper presents a new approach to technology mapping for arbitrary technologies with single outp...
[[abstract]]We study the technology mapping problem for LUT-based FPGAs targeting at power minimizat...
As technology geometries have shrunk to the deep sub-micron (DSM) region, the chip density and clock...
Abstract. Performance of distributed applications largely depends on the mapping of their components...
The rising complexity, customization and short time to market of modern digital systems requires aut...
[[abstract]]In this paper, technology mapping algorithms for minimizing power consumption in FPGA de...
Modern computing chips are composed of multiple, simple, low-power processing cores. Increasing the ...
Research Doctorate - Doctor of Philosophy (PhD)This thesis investigates of the structure and solutio...
The problem of designing individual macrocells for a library with power and speed considerations is ...
[[abstract]]We combine technology mapping and placement into a single procedure, M.map, for the desi...
Field Programmable Gate Array (FPGA)-like programmability and Computer Aided Design (CAD), with Appl...
This paper describes a technique for calculating the switching activity of a set of registers shared...
A combinatorial problem that arises from a novel electronic fabric architecture designed forlow-powe...
Application specific programmable systems are capable of high performance implementations while rema...
[[abstract]]We study the technology mapping problem for LUT-based FPGAs targeting at power minimizat...
This paper presents a new approach to technology mapping for arbitrary technologies with single outp...
[[abstract]]We study the technology mapping problem for LUT-based FPGAs targeting at power minimizat...
As technology geometries have shrunk to the deep sub-micron (DSM) region, the chip density and clock...
Abstract. Performance of distributed applications largely depends on the mapping of their components...
The rising complexity, customization and short time to market of modern digital systems requires aut...
[[abstract]]In this paper, technology mapping algorithms for minimizing power consumption in FPGA de...
Modern computing chips are composed of multiple, simple, low-power processing cores. Increasing the ...
Research Doctorate - Doctor of Philosophy (PhD)This thesis investigates of the structure and solutio...
The problem of designing individual macrocells for a library with power and speed considerations is ...
[[abstract]]We combine technology mapping and placement into a single procedure, M.map, for the desi...
Field Programmable Gate Array (FPGA)-like programmability and Computer Aided Design (CAD), with Appl...
This paper describes a technique for calculating the switching activity of a set of registers shared...