Delay and Power Reduction in Deep Submicron Buses

As technology scales down, coupling between nodes of the circuits increases and becomes an important factor in interconnection analysis. In many cases like the deep submicron technology (DSM), the coupling between lines (inter-wire capacitance) is strong and the energy consumption caused by parasitic capacitance is non-negligible. In this work, we employ the differential low-weight encoding [1] to reduce energy and delay (transmission cost) on DSM buses. We propose an enumeration method that reduces the encoder table-size from O(2n) words to O(n) words, for an n-bit DSM bus, and so reduces the memory complexity significantly and facilitates energy and delay reduction due to addressing and fetching data from large lookup tables. We modify the energy and delay equations for DSM buses and develop new representations in terms of number of the same and opposite direction transitions on the bus and use them in our interconnect analysis. We also use these equations to develop formulas for computing the mean transmission cost per bit on DSM buses for both differential low-weight encoding and uncoded schemes. Using the interconnect analysis, we compute a help codeword (from the set of unselected codewords) on the fly and assign to each selected codeword. This low complexity step consists of simple operations and enables us to gain more cost reduction without increasing the table size or number of the bus lines. The simulation results for 16-bit, 32-bit and 64-bit buses at maximum rate (only one extra line added) show that the proposed encoding scheme achieves more than 10% cost reduction, and performs more than 2.5% better than to the original differential low-weight scheme, in the worst case