Hardness by design technique for field programmable gate arrays.

FPGAs are an attractive alternative for many space-based computing operations. While radiation hardened FPGAs are available, SRAM-based FPGAs are susceptible to Single-Event Upsets (SEUs). Several FPGA design hardening techniques are investigated to improve the reliability of FPGA designs operating in a radiation environment. The improved design reliability provided by these techniques are measured using a single-event upset simulation environment