Monolithic Active Pixel Matrix with Binary Counters in an SOI Process

The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}