Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint

The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350 degrees C, doped layers both p- and n-types, and transparent conducting oxide (TCO)