Implementation of a High Throughput Variable Decimation Pane Filter Using the Xilinx System Generator

In a Synthetic Aperture Radar (SAR) system, the purpose of the receiver is to process incoming radar signals in order to obtain target information and ultimately construct an image of the target area. Incoming raw signals are usually in the microwave frequency range and are typically processed with analog circuitry, requiring hardware designed specifically for the desired signal processing operations. A more flexible approach is to process the signals in the digital domain. Recent advances in analog-to-digital converter (ADC) and Field Programmable Gate Array (FPGA) technology allow direct digital processing of wideband intermediate frequency (IF) signals. Modern ADCs can achieve sampling rates in excess of 1GS/s, and modern FPGAs can contain millions of logic gates operating at frequencies over 100 MHz. The combination of these technologies is necessary to implement a digital radar receiver capable of performing high speed, sophisticated and scalable DSP designs that are not possible with analog systems. Additionally, FPGA technology allows designs to be modified as the design parameters change without the need for redesigning circuit boards, potentially saving both time and money. For typical radars receivers, there is a need for operation at multiple ranges, which requires filters with multiple decimation rates, i.e., multiple bandwidths. In previous radar receivers, variable decimation was implemented by switching between SAW filters to achieve an acceptable filter configuration. While this method works, it is rather ''brute force'' because it duplicates a large amount of hardware and requires a new filter to be added for each IF bandwidth. By implementing the filter digitally in FPGAs, a larger number of decimation values (and consequently a larger number of bandwidths) can be implemented with no need for extra components. High performance, wide bandwidth radar systems also place high demands on the DSP throughput of a given digital receiver. In such applications, the maximum clock frequency of a given FPGA is not adequate to support the required data throughput. This problem can be overcome by employing a parallel implementation of the pane filter. The parallel pane filter uses a polyphase parallelization technique to achieve an aggregate data rate which is twice that of the FPGA clock frequency. This is achieved at the expense of roughly doubling the FPGA resource usage