Identifying the subcircuits in a detailed circuit description is a fundamental operation in both circuit validation and design recovery. Existing identification techniques rely on finding an exact match for a subcircuit structure within the description. These techniques fail to identify subcircuits that are functionally equivalent but have been obfuscated because a different technology is being used or because the design has been optimized. This report presents a mechanism for identifying subcircuits that are functionally equivalent, irrespective of obfuscating details. It also describes the initial progress made in transforming detailed circuit descriptions into corresponding descriptions based on subcircuits. Such progress depends on enum...
One of the directions of logical optimization of multilevel representations of systems of Boolean ...
In this paper we solve the problem of identify-ing a \matching " between two logic circuits or ...
The layout versus schematic (LVS) analysis is an essential part of topology design verification, and...
The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer...
The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer...
Recovering functional information from existing hardware is a difficult problem in design automation...
Recovering functional information from existing hardware is a difficult problem in design automation...
The problem of extracting RTL modules from a gate level netlist has many interesting applications in...
The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microe...
In the literature, it is generally overlooked that designers use functional models more frequently t...
this paper we survey some state-of-the-art techniques used to perform automatic verification of comb...
The problem of converting a flat transistor circuit into a hierarchical circuit of logical gatesis c...
This technical report presents a Binary Decision Diagram (BDD) technique for representing the relati...
In the literature, it is generally overlooked that designers use functional models more frequently t...
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design a...
One of the directions of logical optimization of multilevel representations of systems of Boolean ...
In this paper we solve the problem of identify-ing a \matching " between two logic circuits or ...
The layout versus schematic (LVS) analysis is an essential part of topology design verification, and...
The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer...
The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer...
Recovering functional information from existing hardware is a difficult problem in design automation...
Recovering functional information from existing hardware is a difficult problem in design automation...
The problem of extracting RTL modules from a gate level netlist has many interesting applications in...
The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microe...
In the literature, it is generally overlooked that designers use functional models more frequently t...
this paper we survey some state-of-the-art techniques used to perform automatic verification of comb...
The problem of converting a flat transistor circuit into a hierarchical circuit of logical gatesis c...
This technical report presents a Binary Decision Diagram (BDD) technique for representing the relati...
In the literature, it is generally overlooked that designers use functional models more frequently t...
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design a...
One of the directions of logical optimization of multilevel representations of systems of Boolean ...
In this paper we solve the problem of identify-ing a \matching " between two logic circuits or ...
The layout versus schematic (LVS) analysis is an essential part of topology design verification, and...