Multiplicity-Vertex Detector Electronics Development for Heavy-Ion Detectors

This paper presents the electronics work performed to date for the Multiplicity-Vertex Detector (MVD) for the PHENIX collaboration at RHIC. The detector consists of approximately 34,000 channels of both silicon strips and silicon pads. The per-channel signal processing chain consists of a pre-amplifier gain stage, a current mode summed multiplicity discriminator, a 64 deep analog memory (simultaneous read/write), an analog correlator, and a 10-bit microsecs ADC. The system controller or Heap Manager, supplies all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Prototype performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 mu nwell CMOS process used for fabrication