Design and Implementation of UWB,V-Band and W-Band Low Noise Amplifiers

[[abstract]]本論文以操作頻率在3~10GHz(Ultra-Wideband)，57~64GHz(V-band)以及77~81GHz(W-band)之低雜訊放大器設計與實現為研究目標。研究主題分成三部分： 首先我們使用台積電 0.18 μm CMOS製程設計了一個低雜訊、高增益和出色線性度的寬頻放大器(3~10 GHz)，我們使用了 π-match input network 來達到寬頻與輸入端的匹配，藉由適當的匹配，我們可以的到平坦的高增益與較低的低雜訊,此低雜訊放大器在 3~12.5 GHz頻率下有著平坦增益S21為 13.7±1.5 dB，輸入返回損耗S11低於 -10 dB，以及群延遲變化小於 ±14.6 ps，電路消耗之功率為 18 mW，而3-dB 頻寬可以達到 9.5 GHz。此外在頻帶 3~10 GHz時的雜訊指數為2.4±0.1 dB，而量測所得到的IIP3在6 GHz時為 -2.5 dBm，此顆晶片大小為600.8×662.4mm2(不包含pad面積)。 第二部份為應用於V頻帶系統之57~64 GHz低雜訊放大器。為了縮小晶片面積，我們將電路設計成2級串接放大器，以節省成本，此架構的第一級為共源級放大電路，第二級的架構中我們使用一個疊接放大電路來加強訊號的增益，然後在輸入和輸出端使用T型匹配以得到較好的增益、S參數表現和較低的雜訊。最後在Vdd和Vgs端加上bypass電容使整體電路更為穩定。 最後為應用於 77~81 GHz短距離汽車防撞雷達系統的低雜訊放大器。由於Mos在越高頻的時候寄生電容會越大，而使的增益降低，為了獲得較高的增益，架構上我們使用三個共源級以及做中間級之間的共軛匹配。利用台積電 90 nm CMOS製程實現高增益、超寬頻、低的雜訊的低雜訊放大器。實驗結果3-dB頻寬為12GHz，平坦的增益指數13±0.5 dB，電路功率消耗為21mW，群延遲變化也只有±6.5ps，整體電路特性FOM值為0.8，此結果非常適合應用於77~81GHz的短距離汽車防撞雷達系統。[[abstract]]This thesis aim is to design and implement the low noise amplifier, operating frequency at 3~10GHz (Ultra-wideband)，57~64GHz (V-band) and 77~81GHz (W-band) The thesis can be divided into three parts： In the first part, a low noise figure(NF) and high power gain(S21) 3~10 GHz ultra-wideband low-noise amplifier(UWB LNA) with excellent phase linearity using standard 0.18 um CMOS technology is reported. A π-match input network is used to achieve wideband input impedance matching. Both high and flat S21 and low and flat NF frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA consumes 18 mW, achieving S11 better than -10 dB for frequency lower than 12.2 GHz and group-delay-variation smaller than ±14.6 ps for frequencies 3~10 GHz.Additionally, high and flat S21 of 13.7±1.5 dB is achieved for frequencies 3~12.5 GHz, which means the corresponding 3-dB bandwidth is 9.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.4±0.1 dB for frequencies 3~10 GHz. The measured input third-order inter-modulation point (IIP3) is -2.5 dBm at 6 GHz. The chip area is only 600.8×662.4 mm^2 excluding the test pads. In the second part, a 57~64 GHz low noise amplifier is designed for Vband system. For the sake of reducing chip size and cost, we design a two stage cascade amplifier. In the first stage we use a common source circuit. In order to get sufficient gain, we use a cascode circuit in the second stage. Then we use “T-matching” technique at the input and output term to achieve flat high gain(S21), low noise figure and better “S-Parameter” performances. Finally, we put bypass capacitances at the”Vdd” and “Vgs”term to make our circuit more stable. Finally, a 77~81 GHz low noise amplifier is implemented for the short-range radar system. In order to obtain the high gain and wide bandwidth, we used three common source and conjugate matching techniques between interstage. We design a high gain, wideband and low noise LNA in TSMC 90 nm CMOS technology. The experimental results showed that the 3 dB bandwidth of 12 GHz, flat gain of 13±0.5 dB and power consuming of 21 mW, group-delay-variation of ±6.5 ps, and figure of merit (FOM) is 0.8, this results show that this LNA is suitable for short-range radar systems.[[note]]碩