A High-Speed Low-Voltage Differential-Signal Interface Design

[[abstract]]本篇論文主要研究方向為高速的傳輸介面，利用低電壓差動訊號傳輸技術來達到此目的，它包含傳輸器與接收器兩個部份。在傳輸器部分為了達到高速運作，利用交流耦合提供正回授路徑加快轉換的速度，並且利用電流控制電路節省多餘的電流消耗。在接收器方面為了有較大的共模電壓，採用互補式全差動對。此外，為了加快速度，比較器使用折疊疊接方式做設計。 實作方面以台積電提供的TSMC 0.18μm 1P6M CMOS製程進行設計與下線製作，傳輸器面積275μm × 140μm，接收器面積102μm × 96μm。在速度方面傳輸器與接收器可達到2G/bs，而傳輸器與接收器的功率消耗各為27mW與31mW。[[abstract]]This thesis presents a design of high-speed transmitter and receiver for low-voltage different signaling transmission interface. For achieving high-speed operation, an AC-coupled positive feedback path is added into the transmitter circuit for providing high-speed conversion. In addition a current-control circuit is employed to reduce the power dissipation. The receiver uses a complementary differential pair to get a wide range of common voltage. Furthermore, a folded-cascode type comparator is used for high speed operation. A chip including the circuits of transmitter and receiver was implemented and verified by using TSMC 0.18-μm CMOS technology. The core area of the transmitter and receiver is 275μm × 140μm and 102μm × 96μm, respectively. The transmitter and receiver can operate at 2G/bs. The power consumption of the transmitter and receiver is 27mW and 31mW, respectively.[[note]]碩