Design of Low Power LDO for 2.45GHz Passive RFID Transponder

[[abstract]]在本論文中，設計與實現一個應用在2.45GHz被動式RFID詢答器的低壓降穩壓器。所設計的穩壓器包含有啟動電路、誤差放大器、參考電壓源電路、回授分壓電阻與功率傳輸元件。由於此穩壓系統設計應用在被動式詢答器中，能源是由天線接收射頻訊號，在功率受限與雜訊干擾的情形之下，因此設計重點是在低功率消耗下輸出穩定電壓提供詢答器內電路的電源。模擬結果顯示吾人所設計提供穩壓器使用的參考電壓源電路輸出電壓477mV，功率消耗為611.9nW。穩壓器在電源電壓為1.2V至1.85V時輸出穩定的1V電壓，線性調節率為0.15mV/V，負載調節率為0.37mV/mA，功率消耗為1.17μW。晶片採用國家晶片系統中心(CIC)提供的TSMC 0.18μm 1P6M CMOS製程進行設計與實現，詢答器晶片面積大小為645μm × 615μm，其中穩壓器面積大小為185μm × 150μm。[[abstract]]In this thesis, a Low Power low-dropout voltage regulator application on 2.45GHz passive RFID transponder is presented. The LDO consists of a start-up circuit, error amplifier, voltage reference generator, feedback network, and power transistor. The objective of LDO is to achieve lower power consumption while supply more stable output voltage for RFID transponder under limited and noisy input power extracted from the incident RF signal. Simulations show that the proposed voltage reference for LDO generates a mean reference voltage of about 477mV with power consumption of only 611.9nW. The LDO used the voltage reference outputs a stable 1V with line regulation of 0.15mV/V, load regulation of 0.37mV/mA and power consumption of 1.17μW, when the supply voltage varies from 1.2V to 1.85V. The chip designed uses TSMC 0.18 μm 1P6M CMOS process provided by Chip Implementation Center(CIC). The chip area is 645μm × 615μm with the low-dropout voltage regulator area of 185μm × 150μm.[[note]]碩