Design and Implementation of 3.1-10.6 GHz UWB, 24-GHz, and V-Band CMOS Low Noise Amplifiers

[[abstract]]本論文以超寬頻(Ultra-wideband)低雜訊放大器、24-GHz及V-Band CMOS 低雜訊放大器為研究目標，研究主題分成三部分： 第一部份為應用於接收機超寬頻系統之3.1~10.6 GHz低雜訊放大器。使用Splitting-Load inductive peaking 技術完成3.1~10.6 GHz低雜訊放大器。此技術優點在於使用一個電感達到頻寬延伸、輸入匹配、雜訊指數、低成本；以大幅減少晶片的使用面積。為了達到較小的群延遲變化，在輸出級採用了串聯電感補償技術來增加主極點頻率。並聯電感補償技術則是用來達到輸出匹配。因此；此電路只使用了三個電感。我們使用台積電0.18 mm CMOS製程設計此低雜訊放大器，以探討Splitting-Load inductive peaking 技術是否可以完成上述之總總優點。實驗結果顯示次技術確實可以達到我們預期的特性。3.1~10.6 GHz頻率下有著最高增益S21為12 dB，輸入返回損耗低於-11.2 dB，輸出返回損耗低於-12.2 dB，平坦的雜訊指數3.7~4.9 dB，以及群延遲變化只有± 17.15 ps。此電路消耗之功率為21.8 mW，晶片面積亦只有0.31mm2，非常適合用於整合在系統晶片上。 第二部份為應用於24-GHz短距離汽車防撞雷達系統的低雜訊放大器。使用四個共源級和之間的共軛匹配，獲得最大增益為20 dB。在第二級和第三級採用了電流共用技術來降低電流的消耗；第四級則是靠著回授電阻，以降低供應電壓來達到減少功率消耗。利用台積電0.13 mm CMOS製程實現高增益低雜訊的低雜訊放大器。實驗結果3-dB頻寬為9.4GHz，平坦的雜訊指數3.6~4.1 dB，電路功率消耗為18.8 mW，晶片面積亦只有0.38mm2，群延遲變化也只有± 12.05 ps，整體電路特性FOM值為3.84，此結果非常適合應用於需要高解析度的雷達系統。 最後，使用台積電0.13 mm CMOS製程實現一應用於V頻帶的低雜訊放大器。配合使用電感並聯於高頻，使它共振開路掉雜散電容；此一方法可以增加增益和降低雜訊指數，讓整體的電路只需要四顆電晶體，便有13 dB的增益且3-dB頻寬為7GHz。群延遲變化為± 21.05 ps，輸入返回損耗低於-11.4 dB，輸出返回損耗低於-8.5 dB，非常低的5.7dB雜訊指數和好的-14 dBm的1dB功率輸入增益壓縮點及-3.5 dBm第三階交截點，晶片面積亦只有0.39mm2。根據上述電路特性，非常適合整合於V頻帶的前端接收機中。[[abstract]]This thesis aim is to design ultra-wideband, 24-GHz and V-Band CMOS low noise amplifiers. The theme can be divided into three parts： In the first part, a 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). Splitting-Load inductive peaking techniques realize a 3.1 ~ 10.6 GHz low noise amplifier. The advantages of the circuit are enhanced bandwidth, good input matching, low noise figure, low cost and reduced chip area for using Splitting-Load inductive peaking technique. In order to achieve small group-delay-variation at the same time, in the output stage we increased the frequency of the dominant pole of the LNA. The shunt peaking was for output matching, there we used three inductors for this work. We design LNA in TSMC 0.18 ?m CMOS technology, incorporated with Splitting-Load inductive the peaking technology so we can complete the above numerous merit. The experimental result shows that we achieve our anticipated characteristic with infer technology was presented in our results. High 12dB gain, S11 below -12 dB, S22 below -11.8 dB, flat noise figure of 3.7~ 4.9 dB and the group-delay-variation only ±17.15 ps form 3.1 to 10.6 GHz. The result shows of power consuming 21.8 mW, and chip area only 0.31 mm2, that the LNA is suitable for SOC. In the second part, the 24-GHz low noise amplifier is implemented for the short-range radar system. In order to obtain a high gain of 20 dB, we used four common source and conjugate matching techniques between each stage. The Current-reuse technique is adopted in the third and the fourth stage to reduce power dissipation. In the fourth stage, to further improve the limitations imposed on the supply voltage, the R-feedback circuit is presented in this work. We design high gain and low noise LNA in TSMC 0.13 ?m CMOS technology. The experimental results showed that the 3 dB bandwidth of 9.4 GHz, flat noise figure of 3.6~ 4.1 dB, consuming power of 18.8 mW, chip area of 0.38 mm2, group-delay-variation of ±12.05 ps, and have figure of merit (FOM) of 3.84, The results show that the LNA is suitable for high resolution radar systems. Final, we design a V-band LNA in TSMC 0.13 ?m CMOS technology. Using the shunt inductor at high frequency, the stray capacitance can be opened with LC circuit. This can enhance power gain and decrease noise figure, only four transistors for this work, the circuit can have 13dB gain and 3dB bandwidth of a 7 GHz, S11 below -11.4 dB, S22 below -8.5 dB, a noise figure of 5.7 dB and good P1-dB of -14 dBm and IIP3 of -3.5 dBm at V-band were achieved, chip area only 0.31 mm2. According to the performance, very suitable conformity in V-band front end receiver.[[note]]碩