Design of a Pipelined Analog-to-Digital Converter

[[abstract]]本論文利用TSMC 0.35um 2P4M Mixed Signal的製程設計一個10位元管線式類比數位轉換器，其取樣頻率為50MHz，使用電源供給電壓為3.3V。其架構為九階段(Stage)的管線式類比數位轉換器，前八個階段採用1.5-bit/stage的技術，最後一個階段則為一個2-bit的快閃式類比數位轉換器。取樣電路(S/H)與DAC/減法器/增益級(MDAC)使用開關式電容電路來完成，在取樣保持電路最前端的輸入開關使用拔靴帶式(Bootstrapped)開關電路讓開關的非線性問題降低。最後在所有級數的輸出經由數位錯誤修正電路而得到十位元的數位輸出碼。整體電路的設計採用全差動的架構來降低雜訊的干擾。 依據Hspice模擬結果，整個管線式類比數位轉換器可操作在50MHz之取樣頻率，在1MHz之輸入頻率下，其訊號雜訊失真比為57.94dB，有效位元數為9.33位元，總消耗功率為174mW，整體電路佈局面積為(含PAD)2487.9um*2179.7um。[[abstract]]In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter with TSMC 0.35um 2P4M mixed signal process technology at 3.3V power supply voltage. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt eight conversion stage 1.5-bit per stage technology and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the nonlinearity of input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit. Meanwhile, in order to decrease noise affection, the whole circuit is designed by fully differential structure. According to Hspice simulation result, the designed pipelined ADC can operate at 50MHz. The Signal-to-Noise and Distortion Ratio is 57.94dB when the input frequency is 1MHz and effective number of bit is 9.33-bit. The power dissipation is 174mW. The chip layout area is 2487.9um*2179.7um.[[note]]碩