Design of Low Parasitic Capacitance and Low-power CMOS Capacitive Fingerprint Sensor Readout Circuit

[[abstract]]生物辨識是近年來最熱門的研究議題，而其中最可靠的就是採用指紋辨識。電容式指紋感測器的原理，是藉由量測感測電極板與指紋表面紋路的深淺距離不同，而造成的電容值變化，以此擷取出指紋影像。 在本論文中，我們將會討論低寄生電容與低功率CMOS電容式指紋感測器之研製。藉由新的感測器單元電路佈局安排方法，可以消除寄生電容的影響，並且採用最小尺寸的MOS開關以減少MOS開關的非理想效應，以及獲得良好的電容對電壓轉換特性。而功率消耗方面，則透過控制感測讀取電路中緩衝放大器的靜態消耗電流，以節省功率消耗。 我們採用國家晶片系統設計中心提供的TSMC 0.35μm Mixed-Signal 2P4M CMOS製程，完成32乘32陣列的指紋感測器晶片實作，包含了感測器陣列和周邊控制電路，以及類比至數位轉換器，晶片整體面積為1900μm × 2570μm。晶片工作電壓為3.3V，時脈速度為4MHz。感測電容範圍為0fF至60fF，對應的類比輸出電壓為3.02V至1.57V，以及六位元的數位輸出。晶片整體消耗功率小於5.5mW。[[abstract]]In recent years, Biometric Identification has become the most popular research topic, and one of the most robust methods is fingerprint identification. A capacitive fingerprint sensor acquires the fingerprint image by measuring capacitance variation,caused by different distance between sensing electrode and fingerprint surface. In this thesis, we present a low parasitic capacitance and low-power CMOS Capacitive Fingerprint Sensor Readout Circuit. The effect of parasitic capacitance has been eliminated with novel layout structure in sensor cell, and minimal size switch is used in readout circuit to avoid non-ideal effect of MOS switch and to achieve good C-V characteristic. Power consumption is reduced with quiescent current control in buffer amplifier of readout circuit. A 32x32 fingerprint sensor array is implemented in TSMC 0.35μm Mixed- Signal 2P4M CMOS technology provided by Chip Implementation Center. Including the sensor array, peripheral control circuits and analog to digital converter, the chip area is 1900μm × 2570μm. The chip works at 3.3V power supply and operates at 4MHz clock rate. Capacitance value from 0fF to 60fF can be sensed, corresponding analog output voltage is from 3.02V to 1.57V and the digital output is 6 bits. The overall power consumption is less than 5.5mW.[[note]]碩