A Power-Saving CMOS Level Converter for Dual Supply Voltages

[[abstract]]When using dual supply voltages, the circuit requires level converters at the interface of V(DDH) and V(DDL) gates to block the static current which occurs if a V(DDH) gate drives a V@@ gate. In this paper, a Power-Saving level converter (PSLC) is proposed which has the advantages of low power consumption and high operating speed, and it may operate at different values of V@ ranging from 1.2V to 4.2V. These level converters are simulated for different capacitive loads and operating supply voltage levels using the HSPICE parameters of a 0.35 fim digital CMOS technology. HSPICE simulation results show that an average power saving of 50% and 60% speed increase can be obtained compared to those of the existing technique.Hence, the proposed technique is suited for low power design without degrading performance