Data Access Techniques for Enhanced Energy Efficiency and Performance in In-order Pipelines

Energy efficiency is one of the key metrics in the design of a wide range of processor types. For example, battery powered devices, which are growing in numbers every day, require energy efficient processors to be able to operate for a useful period of time. Techniques that improves the energy efficiency of a processor can alleviate the problems like heat generation to a certain level which in turn can allow to achieve better performance. In addition, energy efficiency reduces the operating costs of high performance computing systems which is very desirable. Level-1 data caches (L1 DC) dissipate a significant portion of the pipeline energy in general purpose processors. For example, L1 DC can dissipate up to 23% of the pipeline energy in a 7-stage single-issue in-order pipeline. In this thesis, a number of techniques are introduced in order to reduce the energy dissipation of L1 DCs. Focus is given to reduce the L1 DC energy without reducing the performance, since L1 DC accesses affect the performance of the processor. Some of the techniques introduced in this thesis can even improve the performance of the processor slightly. In addition, the ease of implementation is one of the important considerations in this thesis, in which the energy saving techniques should be able implementable with the common semi-custom design flows. Some of the proposed techniques reduce the energy dissipation of data translation lookaside buffer (DTLB) which is closely coupled with L1 DC. Two of the papers that are included in this thesis, that is, Speculative Tag Access (STA) and Early Load Data Dependence Detection (ELD^3) are very simple to implement in order to reduce the L1 DC access energy. Another Two papers are included in the thesis are about filter caches, but the main focus is given to the Data Filter Cache (DFC). The first paper tackles the implementation issues related to previously proposed data filter caches and proposes novel ways to utilize DFC in the pipeline to reduce the energy dissipation of both L1 DC and DTLB, but also improve the performance at the same time. The second paper, utilizes filter caches for wide-voltage-range processors in order to tackle the issue of scalability problems of SRAMs used in level-1 caches. A paper about hardware/software co-design technique is introduced to evaluate the potential of software control on the energy efficiency of L1 DC accesses. In the final paper that is included in the thesis, a 7-stage pipeline is evaluated in detail in terms of execute stage and L1 DC access stage which affect the performance directly due to data dependencies