Add to ORKGWe present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL
A delay-locked loop based clock generator with the multiplication ratios from 13 to 20 using a progr...
DoctorIn this thesis, a 40-to-700MHz locking multi-phase DLL, an analysis and design methodology of ...
Delay locked loop is a critical building block of high speed synchronous circuits. An improved archi...
We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock gener...
Delay-locked loops (DLLs) have become ubiquitous in digital circuits. For example, for the last ten ...
A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several n...
[[abstract]]In this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded featur...
Abstract—A new DLL-based approach for all-digital multi-phase clock generation is presented. By usin...
This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for ...
In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock ...
Graduation date: 2012As Moore’s Law continues to give rise to ever shrinking channel lengths, circui...
This paper proposes a new type of delay line locking mechanism with digitally controlled charge tran...
Scaling has been the driving force behind the immense development the field of electronics has seen ...
[[abstract]]In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wid...
High-speed synchronous integrated circuits (ICs), such as microprocessors and memories, require cloc...
A delay-locked loop based clock generator with the multiplication ratios from 13 to 20 using a progr...
DoctorIn this thesis, a 40-to-700MHz locking multi-phase DLL, an analysis and design methodology of ...
Delay locked loop is a critical building block of high speed synchronous circuits. An improved archi...
We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock gener...
Delay-locked loops (DLLs) have become ubiquitous in digital circuits. For example, for the last ten ...
A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several n...
[[abstract]]In this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded featur...
Abstract—A new DLL-based approach for all-digital multi-phase clock generation is presented. By usin...
This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for ...
In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock ...
Graduation date: 2012As Moore’s Law continues to give rise to ever shrinking channel lengths, circui...
This paper proposes a new type of delay line locking mechanism with digitally controlled charge tran...
Scaling has been the driving force behind the immense development the field of electronics has seen ...
[[abstract]]In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wid...
High-speed synchronous integrated circuits (ICs), such as microprocessors and memories, require cloc...
A delay-locked loop based clock generator with the multiplication ratios from 13 to 20 using a progr...
DoctorIn this thesis, a 40-to-700MHz locking multi-phase DLL, an analysis and design methodology of ...
Delay locked loop is a critical building block of high speed synchronous circuits. An improved archi...