Low cost fault handling mechanisms for multicore and many-core systems

2015-02-18As technology scales further down in the nanometer regime, chip manufacturers are able to integrate billions of transistors on a single chip which boost the performance of today‘s multicore and many‐core systems. On the other hand, smaller transistor devices become more vulnerable to various faults due to higher probability of manufacturing defects, higher susceptibility to single event upsets, more process variations and faster wearout rates. Nowadays, computer chips are tested extensively using post‐fabrication process to weed out any chips that do not meet the functional specifications. The chips that meet the functional specifications are then used in building computer systems. Once these systems, particularly in low‐end consumer market segments, enter the in‐field operation they are not actively tested, other than using simple error correcting codes to deal with soft errors. Since reliability is a critical requirement for high‐end mission‐critical systems, they traditionally employ system‐level redundancy for in‐field monitoring and handling of faults. However, technology scaling is expected to make reliability a first‐order concern for the in‐field operation of even low‐end computing systems. Thus, in‐field fault handling mechanisms that can detect, diagnose, recover and tolerate different kinds of faults have to be deployed. ❧ Unlike mission critical systems that can afford expensive fault handling mechanisms, low‐end computing systems are highly cost‐sensitive. As a result, in‐field fault handling mechanisms have to be stringently cost‐effective and should achieve the highest fault coverage for a given area, performance and power overheads. Faults that happen during in‐field operation (i.e. in‐field faults) are classified into three categories: transient, intermittent, and permanent. Specialized fault handling mechanisms can be deployed orthogonally in order to mitigate the effects of the three fault categories. This dissertation presents four techniques for ultra‐low cost in‐field fault handling in chip multiprocessors (CMPs) and many‐core systems such as graphics processing units (GPUs). ❧ In the first part of this dissertation we present SignTest, a usage‐signature adaptive periodic testing mechanism for microprocessors in multicore systems. SignTest strives to reduce the testing energy and time while maintaining high coverage against permanent faults. To achieve this goal, SignTest tracks the usage of the microprocessor functional blocks during every execution epoch and dynamically steers the testing phase according to the usage level of every functional block. The evaluation results show that a conservative implementation of SignTest maintains maximum fault coverage with up to 24% savings in the testing energy and time. Alternatively, a relaxed implementation of SignTest achieves up to 51% savings in the testing energy and time while covering 93% of the expected permanent fault sites. ❧ Once approaches such as SignTest make it feasible to do periodic fault detection at a very low cost, the next concern is how to use the detection outcomes to improve fault diagnosis and recovery. The second part of this dissertation focuses on improving the classification granularity of in‐field faults. A new class of exceptions called reliability‐aware exceptions (RAEs) is proposed. RAEs use a fault history log to classify faults detected in the microprocessor array structures into transient, intermittent, and permanent. Most of the previously proposed approaches classify faults as transient or non‐transient, where all non‐transient faults are handled as permanent faults. But treating all non‐transient faults as permanent faults leads to premature and often unnecessary component replacement demands. Distinguishing intermittent faults and handling them as such improves the effectiveness of fault handling by reducing the performance degradation while simultaneously slowing down device wearout. ❧ The RAE handlers have the ability to manipulate faulty entries in the array structures to recover and tolerate all three categories of faults. For transient faults, the RAE handler leverages the existing roll‐back mechanism to start re‐execution from the instruction which triggers the fault. For intermittent faults, the RAE handler exploits the inherent redundancy in the array structures to de‐configure the faulty entries temporarily. Entries that experience permanent faults are permanently de‐configured. RAEs improve the reliability of the load/store queue (LSQ) and the reorder buffer (ROB) in an out‐of‐order processor by average factors of 1.3 and 1.95, respectively. ❧ The remaining parts of the dissertation present solutions to handle execution faults that occur in throughput‐oriented graphics processing units (GPUs). GPUs are becoming an attractive option to achieve power efficient throughput computing even for general purpose applications that go beyond traditional multimedia workloads. This dissertation presents two GPU‐specific fault handling frameworks which take advantage of massive resource replication present in GPUs to detect, correct, and tolerate faults. ❧ The first framework is Warped-Shield which tolerates permanent (hard) faults in the execution lanes of the GPUs by rerouting computations around faulty execution lanes. Warped-Shield achieves this goal through the following three techniques: thread shuffling, dynamic warp deformation, and warp shuffling. The three techniques work in complementary ways to allow the Warped-Shield framework to tolerate failure rates as high as 50% in the execution lanes with only 14% performance degradation. ❧ Motivated by the insights obtained from Warped-Shield, the last contribution of this dissertation presents Warped-Redundant Execution (Warped-RE) which provides detection and correction for transient, intermittent, and permanent faults in the GPU execution lanes. Warped-Shield assumes that fault locations are identified using other orthogonal approaches, but Warped-RE relies on spatial redundant execution to achieve fault detection and correction. During fault‐free execution, dual modular redundant (DMR) execution is enforced to detect faults. When a fault is detected, triple modular redundant (TMR) execution is activated to correct the fault and identify potential faulty execution lanes. As long as the detected faults are transients, DMR execution is restored after correction is complete. After the first non‐transient fault is detected, TMR execution is retained to guarantee correctness. ❧ To mitigate the high overheads of naïve DMR/TMR execution, Warped-RE leverages the inherent redundancy among threads within the same warp and the underutilization of the GPU execution lanes to achieve low cost opportunistic redundant execution. On average, the performance overhead for DMR execution to detect faults is 8.4%, and once a permanent fault is detected TMR execution overhead is still just 29%