Resiliency-aware scheduling

2013-03-05Hostile environments, shrinking feature sizes and processor aging elicit a need for resilient computing. Traditional course-grained approaches, such as software Checkpoint and Restart (C/R) and hardware Triple Modular Redundancy (TMR), while exhibiting acceptable levels of fault coverage, are often wasteful of resources such as time, device/chip area or power. In order to mitigate these shortcomings, Resiliency-aware Scheduling (RaS), a source-level approach is introduced and described. Resiliency-aware Scheduling combines traditional compiler techniques such as critical path and dependency analysis with the ability to potentially modify the target architecture’s resource configuration. This new approach can, in many cases, offer operational coverage similar to traditional schemes, while enjoying a performance advantage and area savings. ❧ To support Resiliency-aware Scheduling, several novel concepts and contributions are introduced. First, this thesis introduces the concept of Intrinsic Resiliency (IR), a measure of available Temporal Redundancy (TR) due to a computation’s lack of instruction-level parallelism for a fixed set of resources. Second, Hybrid TMR (hTMR), a flexible hardware design scheme that allows for trade-offs between performance and resiliency is presented. By implementing hTMR units, an RaS-hardened design maintains operational coverage while providing more scheduling flexibility, and thereby potentially better performance, than designs using traditional monolithic TMR units. Lastly, two distinct Resiliency-aware Scheduling infrastructures are described: the first based on the Open64 compiler, targeting Field Programmable Gate Arrays (FPGA), and the second based on the Vex compiler toolchains, targeting reconfigurable softcore Very Long Instruction Word (VLIW) architectures. ❧ This thesis also presents promising experimental results from the use of these two infrastructures. For the FPGA target, when using slice Look Up Tables (LUT) as the design metric, the RaS designs synthesized from a test suite of realistic kernel codes were, on average, 19% smaller than the TMR designs with equivalent performance and operational coverage. For the softcore VLIW target, the RaS-hardened executables developed for a case study perform between 15% and 40% faster than a competing software hardening approach. The RaS-derived VLIW executables are also shown to scale better than TMR, with up to a 40% performance improvement over an equivalently sized TMR computation. ❧ While mainstream compilation and synthesis tools exclusively focus on raw execution time or silicon area usage, the increasing rates of soft errors will likely prompt tool designers to focus on error mitigation as an integral part of their design methodologies. The ability to handle resiliency in the same automated fashion as other design attributes, such as area or power consumption, is greatly needed as architectures evolve. The work described here is a first step in this direction