Clustering and fanout optimizations of asynchronous circuits

Restricted until 3 Mar. 2010.As semiconductor technology advances into smaller and smaller geometries, new challenges arise. The increased circuit integration combined with larger variability make it harder for designers to distribute a global clock and global interconnect signals efficiently in their designs. To combat the effects designers use more conservative models and more complicated tools that result in longer design times and diminishing returns from the migration to the smaller geometries. Some of these problems can be addressed by asynchronous circuits, but there exists no welldefined method for automated asynchronous design. Some methods have been proposed over the years, but they leverage off existing synchronous techniques too much, resulting in circuits that are bound by the characteristics of their synchronous counterparts. This thesis proposes a novel approach for generating such circuits, from any arbitrary HDL representation of a circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. The method thus provides a form of automatic pipelining in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. Consequently, the performance can generally maintain or exceed the performance of the original circuit. The method is design-style agnostic and is thus applicable to many asynchronous design styles.; The contributions of the thesis are two-fold. First, we define a model and theoretical infrastructure that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. This provides a framework for proper clustering that can enable the unhindered exploration of area minimization algorithms in the future and lead to optimized competitive designs. Secondly, we propose optimizations to existing slack matching models that take advantage of fanout optimizations of buffer trees that improve the quality of the results