[[abstract]]In this letter, mobility improvements by stress contact etch stop layer (CESL) in a strained 90-nm nMOSFET, with and without notched-gate structure, were studied in detail. Compared to the conventional vertical gate, a device with notched gate shows an extra 7% NMOS ION enhancement for the increased stress in the channel region and the less effect of the halo-implanted impurity on channel. Both simulations with TCAD software and measurements confirm that the notched-gate structure efficiently enhances the generation of high tensile stress on the channel region from the CESL and more localized pocket implant
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop laye...
[[abstract]]This paper reports to improve performances of sub-90 nm CMOSFETs with a notch-gate struc...
[[abstract]]For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on dev...
Novel device architectures offer improved scalability but come often at the price of increased layou...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
Numerical study in conjunction with comprehensive bending experiments has demon-strated that (100)-S...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
ion gate-eff ed w sw fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with f...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
[[abstract]]In this study, we have applied a second high-stress contect etch stop layer (CESL) in ni...
[[abstract]]This study investigates the effects of oxide traps induced by SOI of various thicknesses...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop laye...
[[abstract]]This paper reports to improve performances of sub-90 nm CMOSFETs with a notch-gate struc...
[[abstract]]For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on dev...
Novel device architectures offer improved scalability but come often at the price of increased layou...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
International audienceWe study the effects of a strained contact etch stop layer (CESL) on fully dep...
Numerical study in conjunction with comprehensive bending experiments has demon-strated that (100)-S...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
ion gate-eff ed w sw fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with f...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
[[abstract]]In this study, we have applied a second high-stress contect etch stop layer (CESL) in ni...
[[abstract]]This study investigates the effects of oxide traps induced by SOI of various thicknesses...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop laye...