[[abstract]]For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on device performance and reliability was investigated. In this work, device driving capability can be enhanced with thicker CESL, larger LOD and narrower gate width. With electrical and body potential inspection, serious device’s degradation happened on SOI-MOSFET with narrow gate device because of STI-induced edge current
[[abstract]]The impact of strain induced oxide trap charge on the performance and reliability of con...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
[[abstract]]In this work, the impact of strain engineering on device performance and reliability for...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
[[abstract]]This study investigates the effects of oxide traps induced by SOI of various thicknesses...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
[[abstract]]In this letter, mobility improvements by stress contact etch stop layer (CESL) in a stra...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
The impact of strain induced oxide trap charge on the performance and reliability of contact etch st...
[[abstract]]In this work, for 90nm PD-SOI CMOSFETs on <100> Si substrate, the impacts of high tensil...
[[abstract]]A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL)...
[[abstract]]The impact of strain induced oxide trap charge on the performance and reliability of con...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
[[abstract]]In this work, the impact of strain engineering on device performance and reliability for...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided...
[[abstract]]This study investigates the effects of oxide traps induced by SOI of various thicknesses...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
[[abstract]]In this letter, mobility improvements by stress contact etch stop layer (CESL) in a stra...
[[abstract]]In this letter, we investigate the effects of oxide traps induced by various silicon-on-...
[[abstract]]For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length ...
The impact of strain induced oxide trap charge on the performance and reliability of contact etch st...
[[abstract]]In this work, for 90nm PD-SOI CMOSFETs on <100> Si substrate, the impacts of high tensil...
[[abstract]]A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL)...
[[abstract]]The impact of strain induced oxide trap charge on the performance and reliability of con...
DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based tra...
[[abstract]]In this work, the impact of strain engineering on device performance and reliability for...
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