A New Innovated Design of 40-100V Sided-Isolation NLDMOS with Low Ron for CMOS-compatible(<0.5 micron) Process and Hot Carrier Injection (HCI) Reliability Test

[[abstract]]Sided-Isolation NLDMOS: In intelligent power IC’s, it is very important to get high breakdown with lowest possible specific on-resistance (Rsp) so as to keep heat dissipation as low as possible and thereby enhancing efficiency and reliability. The conventional LDMOS structure still produce high Rsp due to the drift length limit. The newly invented device structure using very short drift length with Sided-Isolation can deliver the world benchmark Rsp performance hence the device can have high efficiency and good reliability performance. So in our new innovated design we invented a good idea that use of Sided-Isolation technique and it will help to keep Rsp very low keeping breakdown still good. In addition added PBL and N-blanket implantation help to have good breakdown, safe operating area(SOA) and sensitivity. N-blanket implantation help to get low NPN beta and this intern help to get better on-state IV performance that is enhanced on-state breakdown as one of the SOA parameter. Added PBL implantation beneath the P-body area helps to get rid of Kirk effect problem in on-state family curves. So by using these techniques we can have optimized best results. The main difficult to get NPN beta less than 1 so that we can able to achieve good On-state performance with best Rsp also. This Sided-Isolation technique helped us to achieve benchmark Rsp performance without compromising the Off-sate breakdown. Hence with all these performance this device become a good solution for smart power applications. Hot Carrier Injection (HCI) Reliability Test: In long time reliability test of the device, the Hot Carriers those gain extra kinetic energy will trapped into the silicon/silicon-di-oxide interface and cause Rsp and Idsat degradation. This mechanism we simulated and tested by using TCAD Sentaurus tool. We used appropriate models to simulate phenomena of charge trapping and degradations that take place in real silicon processes. Electrons that gain high kinetic energy due to applied high electric field will trap into field-oxide region (drift-region) hence Id current will degrade so Rsp and Idsat degrade and Holes gain high kinetic energy will be trap into gate-oxide region causing threshold shift (Vth-shift). We perform HCI reliability test for 40V Sided-Isolation NLDMOS device and measure Id current degradation @vg=5v, Vd=0.1v and Idsat degradation @Vdd=40V and Vg=5v and stress for time 1e3, 1e4, 1e5 seconds and measure corresponding Idsat and Rsp . Hence we can then know and calculate percentage Rsp and Idsat shift. This shift is due to Hot carriers that trapped into Si/Sio2 interface region. We plot and show the trap charges distribution along the interfaces and these trap charges are more with more stress