Reliability Study On 5V BCD CMOS Device: New PMOS-NBTI Characterization And HCI Assessment On NMOS Bend Gate Structure

[[abstract]]In this thesis, reliability assessment for low voltage CMOS device had been studied. New characterization for negative bias temperature instability (NBTI) was proposed using fast triangular pulse with elevated temperature to analyze Si-H bond behavior generating interface trap. Fast triangular pulse was proposed to minimize the recovery effect while the elevated temperature was used to weaken Si-H bond. This proposed measurement technique, shows that threshold voltage shift will be saturated at 3.46mV (0.48% shift) as the device temperature elevated to 400K. For the NMOSFET counterpart, on-resistance (Ron) and drain current saturation (Idsat) degradation due to hot carrier injection HCI stress had been studied for different bend gate structure using three dimensional Technology Computer Aided Design (3D-TCAD) simulator. The amount and distribution of interface trap in the Si/SiO2 interface were also evaluated by 3D simulation for the first time. Compare to conventional strip gate, bend gate structure suffer from higher interface trap generation due to HCI stress which in turn leading to worse Ron and Idsat degradation