In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. With the irruption of multi-cores and parallel applications, this simple interface started to leak. As a consequence, the role of decoupling again applications from the hardware was moved to the runtime system. Efficiently usin...
The expeditious proliferation of Internet connectivity and the growing adoption of digital products ...
This thesis concentrated on the runtime reconfiguration of system-on-chip (SoC) cores to execute spe...
Emerging multi/many-core architectures, targeting both HPC and mobile devices, increase the interes...
In the last few years, the traditional ways to keep the increase of hardware performance at the rate...
In the last few years, the traditional ways to keep the increase of hardware performance to the rate...
The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the perform...
In the last decades, high-performance large-scale systems have been a fundamental tool for scientifi...
Energy efficiency in supercomputing is critical to limit operating costs and carbon footprints. Whil...
Purnaprajna M, Pohl C, Porrmann M, Rückert U. Using Run-time Reconfiguration for Energy Savings in P...
Application-specific multicore architectures are usually designed by using a configurable platform i...
Reconfigurable computing platforms are emerging as the most promising architectures to design genera...
Parallelism is ubiquitous in modern computer architectures. Heterogeneity of CPU cores and deep memo...
Purnaprajna M, Porrmann M. Run-time Reconfigurable Cluster of Processors. In: Proceedings of 41st A...
High performance architectures are constantly evolving in order to deliver ever greater compute powe...
In computing the available computing power has continuously fallen short of the demanded computing p...
The expeditious proliferation of Internet connectivity and the growing adoption of digital products ...
This thesis concentrated on the runtime reconfiguration of system-on-chip (SoC) cores to execute spe...
Emerging multi/many-core architectures, targeting both HPC and mobile devices, increase the interes...
In the last few years, the traditional ways to keep the increase of hardware performance at the rate...
In the last few years, the traditional ways to keep the increase of hardware performance to the rate...
The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the perform...
In the last decades, high-performance large-scale systems have been a fundamental tool for scientifi...
Energy efficiency in supercomputing is critical to limit operating costs and carbon footprints. Whil...
Purnaprajna M, Pohl C, Porrmann M, Rückert U. Using Run-time Reconfiguration for Energy Savings in P...
Application-specific multicore architectures are usually designed by using a configurable platform i...
Reconfigurable computing platforms are emerging as the most promising architectures to design genera...
Parallelism is ubiquitous in modern computer architectures. Heterogeneity of CPU cores and deep memo...
Purnaprajna M, Porrmann M. Run-time Reconfigurable Cluster of Processors. In: Proceedings of 41st A...
High performance architectures are constantly evolving in order to deliver ever greater compute powe...
In computing the available computing power has continuously fallen short of the demanded computing p...
The expeditious proliferation of Internet connectivity and the growing adoption of digital products ...
This thesis concentrated on the runtime reconfiguration of system-on-chip (SoC) cores to execute spe...
Emerging multi/many-core architectures, targeting both HPC and mobile devices, increase the interes...