In Networks-on-Chip (NoC) designs, crosstalk noise has become a serious issue which may cause the communication channel unreliable. The crosstalk problem can be mitigated by wide spacing of serial lines. However, the wider spacing of serial lines will reduce the number of the lines, thus reduce the data throughput. In this paper, a new fully adaptive multi-path routing (MPR) scheme is proposed to maximize the data throughput by utilizing multiple paths for concurrent data transmission. For the proposed MPR algorithm, two transport models are considered: the full-wire-bank transport model (FM) and the half-wire-bank transport model (HM). Theoretical analysis shows that the MPR scheme under both FM and HM achieves improvement in data throughp...
Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integr...
Many different factors, such as topology, routing technique, selection function, flow control policy...
In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm wh...
In Networks-on-Chip (NoC) designs, crosstalk noise has become a serious issue which may cause the co...
In our previous work, a multi-path routing (MPR) scheme was proposed to maximize the data throughput...
With the continuously increasing number of cores, on-chip communication has gained a significant rol...
For most of the history of computing, transistors have been expensive while wires have been cheap. C...
Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of ...
Networks-on-chip have evolved as the natural solution for a scalable interconnect that can be automa...
With the increasing number of processing cores in many- core chip-multiprocessors (CMPs) and with th...
The overall performance of Multi-Processor System-on-Chip (MPSoC) platforms depends highly on the ef...
As the technology is scaling, reducing wire delays is the major hurdle in increasing communication s...
Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a lar...
Abstract: In this paper, we present several enhanced network techniques which are appropriate for VL...
As technology geometries have shrunk to the deep submicron regime, the communication delay and power...
Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integr...
Many different factors, such as topology, routing technique, selection function, flow control policy...
In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm wh...
In Networks-on-Chip (NoC) designs, crosstalk noise has become a serious issue which may cause the co...
In our previous work, a multi-path routing (MPR) scheme was proposed to maximize the data throughput...
With the continuously increasing number of cores, on-chip communication has gained a significant rol...
For most of the history of computing, transistors have been expensive while wires have been cheap. C...
Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of ...
Networks-on-chip have evolved as the natural solution for a scalable interconnect that can be automa...
With the increasing number of processing cores in many- core chip-multiprocessors (CMPs) and with th...
The overall performance of Multi-Processor System-on-Chip (MPSoC) platforms depends highly on the ef...
As the technology is scaling, reducing wire delays is the major hurdle in increasing communication s...
Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a lar...
Abstract: In this paper, we present several enhanced network techniques which are appropriate for VL...
As technology geometries have shrunk to the deep submicron regime, the communication delay and power...
Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integr...
Many different factors, such as topology, routing technique, selection function, flow control policy...
In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm wh...