An Easy Tune-up Exponentially Fast Annealer for High-quality Analog Module Placement

VLSI analog module placement problem is NP-complete, and both simulated Cauchy annealing and simulated Boltzmann annealing approaches are widely employed as the search engine nowadays. These approaches, however, exhibit low execution efficiency and pose high degree of difficulty in tuning. In this paper, we present a very fast simulated re-annealing placement algorithm for analog VLSI layout design. We show that this algorithm is exponentially faster than either Cauchy or Boltzmann annealing. The functionality of the re-annealing is to perform an adaptive control on the annealing schedules of multidimensional parameters. Moreover, a cell-slide-based flat placement style satisfying various symmetry constraints pertaining to analog layout design is developed to drastically reduce the solution space without degrading the search opportunities. The dedicated cost function covers the special requirements for analog integrated circuits, including area, wire length, aspect ratio, proximity, parasitic effects, etc. The proposed algorithm has been applied to layout several analog circuits, and it appears superior to the conventional approaches with significantly less amount of CPU time