Heterogeneous Embedded Network Architecture

In this thesis we focused on high performance embedded real-time networks which are designed for systems like radar signalling processing systems, control systems etc. These high performance embedded networks consist of emerging standards like PCI Express, RapidIO, and standard Ethernet. All of these switched embedded networks communicate with each other through common gateway nodes. As these networks have different rate characteristics, maximum packet size (MTU), packet priorities, addressing schemes etc we have therefore defined the gateway nodes for these heterogeneous embedded networks which will allow these heterogeneous embedded networks to communicate with each other with the help of different translation functions. These gateway nodes allow end-to-end transmission across the heterogeneous embedded networks while keeping bound on end-to-end delay and guaranteed throughput. We need to have some flow control mechanism which will shape the traffic flow in the mentioned embedded networks and will avoid from buffer overflow