A reconfigurable SIMD architecture on-chip

This project targets the problems with design and implementation of Single Instruction Multiple Data (SIMD) architectures in System-on-Chip (SoC), with the goal to construct a reconfigurable framework in VHDL to ease this process. The resulting framework should be implemented on an FPGA and its usability tested. The main parts of a SIMD archi- tecture was identified to be the Control Unit (CU), the Processing Elements (PE) and the Interconnection Network (ICN), and a framework was constructed with these parts as the main building blocks. The constructed framework is reconfigurable in data width, memory size, number of PEs, topology and instruction set. To test ease of use and per- formance of the system a FIR-filter application was implemented. The scalability of the system and its different parts has been measured and comparisons are illustrated