Discrete wavelet transform architecture for image coding and decoding

This thesis analyses and implements a Discrete Wavelet Transform (DWT) architecture for image processing. The architecture comprises two modules, one for image coding and the other for image decoding. Each module is implemented using a novel Modified Forward-Backward Register Allocation (MFBRA) method and accommodates two Fast Processing Elements (FPE). The resulting architecture minimizes the hardware required to perform the task together with reduced processing time, rendering the whole structure suitable for real time applications. The whole architecture is implemented and simulated using the Verilog Hardware Description Language