Analysis of novel high-performance switch architectures for broadband-ISDN.

In this thesis, we present an analysis of three novel switch architectures for Broadband-ISDN using the Asynchronous Transfer Mode (ATM). Our focus is on high-performance switch architectures, which have low to medium hardware complexity. The first switch architecture presented is a speed-up switch with input and output buffers, where a back-pressure mechanism is applied to avoid packet loss at the output buffers. We examine the maximum throughput, mean delay and packet loss rate at the input buffers of this speed-up switch. The switch with a speed-up of 3, and 20 buffers at each output port can achieve a maximum throughput of 90% or more. These results are of a great practical value since a switch with high speed-up is difficult to realize. A simple implementation of the switch is also presented. The second switch architecture, called Limited Intermediate Buffer (LIB) switch, is based on a crossbar switch fabric. A buffer to store a single packet is provided at each crosspoint of this switch. In addition to this, buffers are provided at the input ports to reduce the packet loss. We propose a new scheduling policy called head-of-line priority selection, which reduces the head-of-line blocking and thus improves the performance of the LIB switch substantially. A 16 x 16 switch under uniform random traffic can achieve a throughput of 87.5%. A three-stage interconnection network consisting of symmetric and asymmetric LIB switch modules is also presented. The simulation results of the interconnection network prove the efficacy of the LIB switch architecture and the proposed head-of-line priority selection scheme. Finally, the handling of delay and loss sensitive traffic in ATM networks is discussed. To keep the protocols simple at the ATM layer, we suggest that the handling of these priorities should be de-linked. The performance of two classes of delay-sensitive traffic in an input buffered nonblocking switch architecture is analyzed. The result of the analysis under two different non-preemptive priority schemes suggests that, to reduce the hardware complexity, the packets should not be distinguished based on their priority within the switch fabric. To overcome the throughput limitation of the input buffered switch, a dual plane switch architecture is presented, where each plane is a nonblocking switch with input buffers