[[abstract]]In this paper, a new structure of the nonlinear PFD is proposed to achieve fast lock as well as small output jitter. The proposed Piecewise-Linear PFD has more flexibility than previous designs, since the lock time and the output jitter of the PLL are no longer tradeoffs. When the phase difference of the reference and the feedback signal is larger than π, additional charging or discharging current is injected to the loop filter (LF) to accelerate the lock process. On the other hand, to keep the jitter small, the Piecewise-Linear PFD acts just like the conventional linear PFD while approaching lock. The post-simulation results show that a speedup of 68% can be achieved with comparison to the conventional PLL. Moreover, the jitter...
This paper describes two novel phase-frequency detectors. The first one overcomes the non-linear tra...
Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can ...
In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acqui...
A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phas...
The delay of the reset path, needed to eliminate the dead zone problem in a conventional three-state...
[[abstract]]A dual-slope frequency detector and charge pump architecture to achieve fast locking of ...
Abstract:- In this paper, we propose a new phase-locked loop design with both a high speed phase fre...
Abstract—Phase locked loops find wide application in several modern applications mostly in advance c...
Many good phaselocked loops (PLL) books exist. However, how to acquire the input frequency from an u...
[[abstract]]For high speed and low jitter PLL application, a new phase frequency detector (PFD) with...
International audienceSynchronization is a critical operation in digital communications. An importan...
This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL)...
In this paper we present a design of adaptive gain phase-locked loop(PLL) which features fast acquis...
Abstract — This paper describes two novel phase-frequency detectors. The first one overcomes the non...
129-133<span style="font-size:12.0pt;line-height:115%; font-family:" calibri","sans-serif";mso-asci...
This paper describes two novel phase-frequency detectors. The first one overcomes the non-linear tra...
Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can ...
In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acqui...
A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phas...
The delay of the reset path, needed to eliminate the dead zone problem in a conventional three-state...
[[abstract]]A dual-slope frequency detector and charge pump architecture to achieve fast locking of ...
Abstract:- In this paper, we propose a new phase-locked loop design with both a high speed phase fre...
Abstract—Phase locked loops find wide application in several modern applications mostly in advance c...
Many good phaselocked loops (PLL) books exist. However, how to acquire the input frequency from an u...
[[abstract]]For high speed and low jitter PLL application, a new phase frequency detector (PFD) with...
International audienceSynchronization is a critical operation in digital communications. An importan...
This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL)...
In this paper we present a design of adaptive gain phase-locked loop(PLL) which features fast acquis...
Abstract — This paper describes two novel phase-frequency detectors. The first one overcomes the non...
129-133<span style="font-size:12.0pt;line-height:115%; font-family:" calibri","sans-serif";mso-asci...
This paper describes two novel phase-frequency detectors. The first one overcomes the non-linear tra...
Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can ...
In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acqui...