A Compromise between Speed and Complexity in a BCD Adder

[[abstract]]This paper presents a logic design for a new decimal-digit parallel adder. The output decimal carry delay time is reduced and the addition speed of two BCD numbers is improved. The inter-stage output carries of a binary adder are essentially eliminated. Also the hardware is economized. The corrected decimal sums and output carry are produced simultaneously, in contrast with the conventional method, whose decimal sums are delayed utter the output carry.[[fileno]]2030129010017[[department]]電機工程學