[[abstract]]In this paper we propose a method for generating test patterns very efficient for stuck-at faults, either in symmetric or unsymmetric circuits. The faulty symbol D or D is distributed like any binary variable, from the site of source to the primary output passing through all possible paths. The test pattern for the stuck-at fault is generated by only one backtrack and simultaneously determined whether the test pattern exists or not. There is therefore no need for tracing paths forwards and backwards several times as the conventional D-algorithm or the modified version of D-algorithm during the process of the test pattern generation.[[fileno]]2030129010009[[department]]電機工程學
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 1406-0175We propose a new approach...
Diagnosis is an important but difficult problem in the design and manufacturing of VLSI circuits. Th...
An efficient method is proposed for detecting hard- to-detect stuck-at faults of combinational circu...
Testing of combinational circuit is crucial important to ensure high level of functionality. As dens...
This paper presents a new method to generate test patterns for multiple stuck-at faults in combinati...
In combinational logic circuits, stuck-at faults are permanent faults that are modelled as logical p...
We propose a procedure for determining fault detection tests for single and multiple fault in combin...
A 16-valued logic system for testing combinational circuits is presented. This logic system has been...
A 16-valued logic system for testing combinational circuits is presented. This logic system has been...
In combinational logic circuits the generation of complete fault detection test sets requires the de...
To produce reliable electronic systems, defect-free components must be available. Automatic test pat...
Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip man...
An efficient method is proposed for detecting hard- to-detect stuck-at faults of combinational circu...
A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes...
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 1406-0175We propose a new approach...
Diagnosis is an important but difficult problem in the design and manufacturing of VLSI circuits. Th...
An efficient method is proposed for detecting hard- to-detect stuck-at faults of combinational circu...
Testing of combinational circuit is crucial important to ensure high level of functionality. As dens...
This paper presents a new method to generate test patterns for multiple stuck-at faults in combinati...
In combinational logic circuits, stuck-at faults are permanent faults that are modelled as logical p...
We propose a procedure for determining fault detection tests for single and multiple fault in combin...
A 16-valued logic system for testing combinational circuits is presented. This logic system has been...
A 16-valued logic system for testing combinational circuits is presented. This logic system has been...
In combinational logic circuits the generation of complete fault detection test sets requires the de...
To produce reliable electronic systems, defect-free components must be available. Automatic test pat...
Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip man...
An efficient method is proposed for detecting hard- to-detect stuck-at faults of combinational circu...
A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes...
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 1406-0175We propose a new approach...
Diagnosis is an important but difficult problem in the design and manufacturing of VLSI circuits. Th...