[[abstract]]We consider energy consumption during testing for C-testable iterative logic arrays (ILAs). We show that the cell test sequences in the ILA have a property of repetition and ensure that the test energy depends on the order of the test patterns, which is obvious for random logic, but is not for ILAs due to its iteration property. The time complexity for obtaining the transition energy of all possible pattern sequences is reduced from O((XNC2)-N-2-C-2) to O((XC2)-C-2), where X, N, and C represent the test length, array size, and cell complexity, respectively. We formulate the problem of finding the optimal test sequence, as a shortest-path problem. Using the obtained test sequence the total energy consumption is minimized, and the...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
This paper presents a new technique for power minimization during test application in sequential cir...
The use of regular logic structures has become very important in the recent past due to the complexi...
[[abstract]]© 1997 Institute of Electrical and Electronics Engineers -Deterministic test patterns of...
[[abstract]]© 1995 Institute of Electrical and Electronics Engineers - A design-for-testability (DFT...
In this work, measures to evaluate fault-effect propagation of test patterns of a C-test are first f...
AbstractThe test methods of two-dimensional (2-D) iterative logic arrays (ILAs) composed of combinat...
[[abstract]]C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault...
Power minimization and test length reduction are two objectives for BIST (Built-In-Self-Test). To re...
ISBN: 0780306236The author shows that, if the number of the states of the reduced flow table of an i...
Test Pattern Generation for combinational circuits entails the identification of primary input assig...
Abstract:- In today’s nanometer technology era, more sophicated defect mechanisms might exist in the...
[[abstract]]A new design to reduce the overhead required for a fully testable PLA is proposed. This ...
113 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The test methods of general i...
A question is considered as to the development of a procedure of testing combinational circuits with...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
This paper presents a new technique for power minimization during test application in sequential cir...
The use of regular logic structures has become very important in the recent past due to the complexi...
[[abstract]]© 1997 Institute of Electrical and Electronics Engineers -Deterministic test patterns of...
[[abstract]]© 1995 Institute of Electrical and Electronics Engineers - A design-for-testability (DFT...
In this work, measures to evaluate fault-effect propagation of test patterns of a C-test are first f...
AbstractThe test methods of two-dimensional (2-D) iterative logic arrays (ILAs) composed of combinat...
[[abstract]]C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault...
Power minimization and test length reduction are two objectives for BIST (Built-In-Self-Test). To re...
ISBN: 0780306236The author shows that, if the number of the states of the reduced flow table of an i...
Test Pattern Generation for combinational circuits entails the identification of primary input assig...
Abstract:- In today’s nanometer technology era, more sophicated defect mechanisms might exist in the...
[[abstract]]A new design to reduce the overhead required for a fully testable PLA is proposed. This ...
113 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.The test methods of general i...
A question is considered as to the development of a procedure of testing combinational circuits with...
As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random de...
This paper presents a new technique for power minimization during test application in sequential cir...
The use of regular logic structures has become very important in the recent past due to the complexi...