[[abstract]]The authors extend the Shen-Ferguson approach (1984) of testing carry-save (CS) array multipliers to the testing of four other practical cellular array multipliers commonly used in digital signal processing: (1) the modified CS array multiplier without primary carry inputs is shown to be C-testable at the expense of only two extra input pins; (2) the pipelined (systolic) array multiplier, which differs from the CS array multiplier in the additional latches between adjacent cells, is C-testable by modifying the cell function in the same way; (3) the two's-complement pipelined multiplier works as well; (4) the operand-resident multiplier is shown to be C-testable partly by truth-table modification and, partly, by scan path design[...
[[abstract]]© 1995 Institute of Electrical and Electronics Engineers - A design-for-testability (DFT...
International audienceThis paper describes an approach for testing a class of programmable logic dev...
Reconfigurable devices used in digital signal processing applications must handle large amounts of d...
[[abstract]]Presents an application-specific computer-aided design (ASCAD) tool that aids the design...
[[abstract]]Design-for-testability techniques and built-in self-test structures are presented for ce...
This paper presents several new array multiplier architectures for reducing the switching activity i...
[[abstract]]© 1996 Institution of Engineering and Technology-By utilizing the don't care minter...
[[abstract]]C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault...
: This paper deals with the test of an integrated on-line multiplier suitable for very large numbers...
The main objective of this project is to design testability features that can potentially be include...
This thesis illustrates the usefulness of the full adder as the elementary cell for designing cellul...
ISBN: 3540584196This paper describes an approach for testing a class of programmable logic devices c...
Conventional array multiplier based on carry save adders is optimized in this letter. Some specific ...
In this paper we propose the design of an easily testable, with respect to path delay faults, n*m ca...
The authors compare various array multiplier architectures based on (p,q) counter circuits. The trad...
[[abstract]]© 1995 Institute of Electrical and Electronics Engineers - A design-for-testability (DFT...
International audienceThis paper describes an approach for testing a class of programmable logic dev...
Reconfigurable devices used in digital signal processing applications must handle large amounts of d...
[[abstract]]Presents an application-specific computer-aided design (ASCAD) tool that aids the design...
[[abstract]]Design-for-testability techniques and built-in self-test structures are presented for ce...
This paper presents several new array multiplier architectures for reducing the switching activity i...
[[abstract]]© 1996 Institution of Engineering and Technology-By utilizing the don't care minter...
[[abstract]]C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault...
: This paper deals with the test of an integrated on-line multiplier suitable for very large numbers...
The main objective of this project is to design testability features that can potentially be include...
This thesis illustrates the usefulness of the full adder as the elementary cell for designing cellul...
ISBN: 3540584196This paper describes an approach for testing a class of programmable logic devices c...
Conventional array multiplier based on carry save adders is optimized in this letter. Some specific ...
In this paper we propose the design of an easily testable, with respect to path delay faults, n*m ca...
The authors compare various array multiplier architectures based on (p,q) counter circuits. The trad...
[[abstract]]© 1995 Institute of Electrical and Electronics Engineers - A design-for-testability (DFT...
International audienceThis paper describes an approach for testing a class of programmable logic dev...
Reconfigurable devices used in digital signal processing applications must handle large amounts of d...