Resilient Self-V-DD-Tuning Scheme With Speed-Margining for Low-Power SRAM

[[abstract]]Lowering the supply voltage is an effective way to significantly reduce the power consumption of a Static Random Access Memory (SRAM). However, the minimum supply voltage (V-minf) required to support a given operating frequency in an SRAM macro is often elusive from one chip to another due to process variations. Moreover, temperature could vary when an SRAM macro is in operation, and thus exacerbating the problem since temperature variation could affect the V-minf. In this paper, we propose an on-chip self-V-DD-tuning scheme that automatically adjusts each manufactured SRAM macro to a minimal voltage near its V-minf. Our scheme can provide a user-specified speed margin (e.g., 10% of the target frequency), and thereby creating a guard band for assuring robust operations over a wide range of temperatures. Simulation results show that, with the proposed speed margining technique, a 64 Kb SRAM macro can tolerate temperature up to 125 degrees C. Measurement results from a test chip in a 0.18-mu m CMOS process also demonstrate that we can achieve 40% power savings for an 8 Kb SRAM macro operating at 150 MHz by means of this resilient self-V-DD-tuning.[[fileno]]2030116010029[[department]]電機工程學