[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on transistors in subthreshold operation. The WTA adapts a tree structure to reduce the effect of process variations. In addition to the traditional way of using positive feedback to improve the comparison performance, we propose to use translinear loop to amplify the difference between two inputs before comparison to achieve high resolution. The circuit has been fabricated with TSMC 0.35μm 2P4M process. The WTA operates with input current as low as a few nano amperes and resolution as high as 0.1%. Measurement results show that the circuit has a non-negligible offset. Discussions on the source of the offset with a proposed solution are also gi...
In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with ...
This paper presents the design of a closed-loop time difference amplifier (TDA) with a novel self-ca...
This paper presents an efficient and robust circuital implementation of a rail-to-rail input stage w...
[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on...
The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell t...
Abstract In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit ...
A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As co...
A new current-mode maximum winner-take-all (Max WTA) circuit is presented. Inputs and output of the ...
This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimu...
Abstract This letter presents an upgraded winner‐take‐all (WTA) circuit that is capable of operating...
This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA)...
The linear range of approximately ±75mV of traditional subthreshold transconductance amplifiers is t...
This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily ...
We have designed, fabricated, and tested an adaptive Winner-Take-All (WTA) circuit based upon the cl...
Abstract. In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O(n) complex...
In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with ...
This paper presents the design of a closed-loop time difference amplifier (TDA) with a novel self-ca...
This paper presents an efficient and robust circuital implementation of a rail-to-rail input stage w...
[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on...
The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell t...
Abstract In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit ...
A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As co...
A new current-mode maximum winner-take-all (Max WTA) circuit is presented. Inputs and output of the ...
This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimu...
Abstract This letter presents an upgraded winner‐take‐all (WTA) circuit that is capable of operating...
This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA)...
The linear range of approximately ±75mV of traditional subthreshold transconductance amplifiers is t...
This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily ...
We have designed, fabricated, and tested an adaptive Winner-Take-All (WTA) circuit based upon the cl...
Abstract. In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O(n) complex...
In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with ...
This paper presents the design of a closed-loop time difference amplifier (TDA) with a novel self-ca...
This paper presents an efficient and robust circuital implementation of a rail-to-rail input stage w...