An Low-Jitter All-Digital Phased-Locked Loop Using a Suppresive Digital Loop Filter

[[abstract]]In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1 ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications. In order to reduce output clock jitter after phase locking, we propose a three-step locking procedure. The phase can be locked quickly through a preliminary phase locking scheme and the jitter is then reduced by the proposed suppressive digital loop filter. Simulation results show the jitter performance is very close to that of free running DCO. The jitterPk-Pk and jitterRMS is 51 ps and 6.74 ps respectively when the output clock of ADPLL operates at 200 Mhz.[[fileno]]2030172030046[[department]]電機工程學