An Analytical Model of HBM ESD Current Distribution and Modified ESD Protection Structure

[[abstract]]In order to study the ESD zapping current distribution variation with the well pick-up layout, a new transmission-line equivalent-circuit model is proposed which includes the effects of parasitic bipolar transistors and the horizontal and vertical P-well resistance. Based on this equivalent circuit and from real-time I-V characteristics during ESD zapping (Duvvury and Diaz, 1992), an analytical solution can be derived. For conventional multi-finger structures, it shows that the maximum current or power density of the device under the ESD zapping event is located at the region near the P-well pick-up. This model prediction is consistent with the device's damage sites after ESD zapping. Based on this model, a novel protection structure leading to uniform current distribution can be achieved by inserting P+ diffusion into each source region of NMOS devices. From the real-time I-V characteristics during ESD zapping, a new phenomenon termed the self-biasing effect is also observed. In order to sustain sufficient substrate potential to keep the bipolar turn-on, the device's snapback voltage should increase to generate more impact ionization current when the effective substrate resistance decreases. We observed the phenomenon that snapback voltage is varied with the device layout. As a result, higher snapback voltage may not lead to lower ESD threshold voltage[[fileno]]2030170030053[[department]]電機工程學