Efficient VLSI architectures for HDTV subband filter banks

[[abstract]]The authors develop two efficient VLSI architectures for the non-separable 2-D perfect reconstruction (PR) filter proposed by G. Karlsson and M. Vetterli (1990). By fully utilizing the special relation among their coefficients and nicely arranging the data flow, they construct the whole filter bank via a single prototype filter. Therefore, the expense of arithmetic units is reduced to about one quarter of the original. Furthermore, the data rate for the proposed architecture is also reduced to one quarter of the input data rate. As a result, with 1.2 μm CMOS technology, the speed requirement is easily achieved. In addition, the whole filter bank can be implemented within a single-chip for HDTV applications[[fileno]]2030101030003[[department]]電機工程學