[[abstract]]As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current. In previous works, a single body biasing is applied to whole circuit. In a slow circuit, since the FBB is applied to whole circuit, the leakage current increases dramatically. In a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body biasing is restri...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-st...
In this paper, we investigate electrical effects of transistor layout shape (both in the channel and...
[[abstract]]As fabrication technology progresses, several new challenges follow. Among them, the mos...
[[abstract]]In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As s...
We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage cu...
Leakage power minimization has become an important issue with technology scaling. Variable threshold...
Abstract-Leakage current is susceptible to variation of transistor parameters and environment such a...
In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most impo...
In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most impo...
With the technology process scaling, leakage power dissipation is becoming a growing number of perce...
Abstract — In recent years, sub-threshold logic and body bias technique provides ultra low power and...
bias voltage, subthreshold leakage, Band-to-band tunneling leakage, gate tunneling leakage, 32nm CMO...
Abstract — We propose a fine-grained scheme to compensate for within-die variations in dynamic logic...
Abstract — This paper describes a new power minimizing method by optimizing supply voltage control a...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-st...
In this paper, we investigate electrical effects of transistor layout shape (both in the channel and...
[[abstract]]As fabrication technology progresses, several new challenges follow. Among them, the mos...
[[abstract]]In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As s...
We present techniques to determine the optimal body bias (forward or reverse) to minimize leakage cu...
Leakage power minimization has become an important issue with technology scaling. Variable threshold...
Abstract-Leakage current is susceptible to variation of transistor parameters and environment such a...
In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most impo...
In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most impo...
With the technology process scaling, leakage power dissipation is becoming a growing number of perce...
Abstract — In recent years, sub-threshold logic and body bias technique provides ultra low power and...
bias voltage, subthreshold leakage, Band-to-band tunneling leakage, gate tunneling leakage, 32nm CMO...
Abstract — We propose a fine-grained scheme to compensate for within-die variations in dynamic logic...
Abstract — This paper describes a new power minimizing method by optimizing supply voltage control a...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse...
This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-st...
In this paper, we investigate electrical effects of transistor layout shape (both in the channel and...