Logic and fault simulation by cellular automata

[[abstract]]We propose a massively parallel architecture to speed up the logic and fault simulation. We use a 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms the previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS.[[fileno]]2030108030102[[department]]電機工程學